The AD9847 is a highly integrated CCD signal processor for digital still camera applications. The AD9847 includes a com-plete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with approximately 500 ps
resolution at clock speeds of 40 MHz.
The AD9847 is specified at pixel rates of 40 MHz. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 10-bit A/D converter. The timing driver provides the high speed CCD clock drivers for RG and H1H4. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving 48-lead LQFP, the AD9847 is speci-fied over an operating temperature range of 20°C to +85°C.
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Digital Still Cameras
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Correlated Double Sampler (CDS)2 dB to +10 dB Pixel Gain Amplifier (PxGA®)2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)10-Bit 40 MHz A/D ConverterBlack Level Clamp with Variable Level ControlComplete On-Chip Timing DriverPrecision Timing™ Core with 500 ps Resolution at 40 MSPSOn-Chip 5 V Horizontal and RG Drivers48-Lead LQFP Package
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AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . .0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . .0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . .0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . ... 0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 ....... 0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . 0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . .....0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . ..... 0.3 to AVDD + 0.3 V
BYP13, CCDIN to AVSS . . . . . .... . . 0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . .300°C
Post a Buying Lead
Required Field 
